Abstract:
Present Field Programmable Gate Array (FPGA)
manufacturers incorporate multi-millions of logic resources
which enables hardware designers to design applications extending
to large scales. However, handling such applications by
existing FPGA Computer Aided Design (CAD) flow requires
more improvement in terms of area, performance and power
efficiency considerations. The current CAD flow requires the
input design to be in Register Transfer Level (RTL). RTL
input designs limit the design productivity only to hardware
experts in performing analysis for various optimisations. Optimising
RTL designs manually are increasingly hard. High-
Level Synthesis (HLS) is an approach capable of increasing
the design productivity of hardware applications compared to
commonly used Hardware Description Languages (HDLs) and is
known to be an intelligent approach for performing optimisations
at a higher level of abstraction. In this paper, an approach
that follows the HLS flow to cater to the mapping of FPGA
applications in a power efficient manner using a communicationaware
partitioning strategy is proposed. From experiments, it was
possible to achieve an average reduction of 8.39% routing thermal
power and 3.34% total power using the proposed approach
