dc.contributor.advisor |
Pasqual, AA |
|
dc.contributor.advisor |
Rodrigo, R |
|
dc.contributor.author |
Samarawickrama, MG |
|
dc.date.accessioned |
2011-04-06T08:46:34Z |
|
dc.date.available |
2011-04-06T08:46:34Z |
|
dc.identifier.uri |
http://dl.lib.mrt.ac.lk/handle/123/741 |
|
dc.description |
CD-ROM included ; A thesis submitted to the Department of Electronic and Telecommunication Engineering for the MSc in Electronic and Telecommunication Engineering |
en_US |
dc.description.abstract |
The modern FPGAs enable system designers to develop high-performance com- puting (HPC) applications with large amount of parallelism. Real-time image processing is such a requirement that demands much more processing power than a conventional processor can deliver. In this research, we implemented software and hardware based architectures on FPGA to achieve real-time image processing. Furthermore, we benchmark and compare our implemented architectures with ex- isting architectures. The operational structures of those systems consist of on-chip processors or custom vision coprocessors implemented in a parallel manner with e cient memory and bus architectures. The performance properties such as the accuracy, throughput and e ciency are measured and presented.// According to results, FPGA implementations are faster than the DSP and GPP implementations for algorithms which can exploit a large amount of parallelism. Our image pre-processing architecture is nearly two times faster than the opti- mized software implementation on an Intel Core 2 Duo GPP. However, because of the higher clock frequency of DSPs/GPPs, the processing speed for sequential computations on on-chip processors in FPGAs is slower than on DSPs/GPPs. These on-chip processors are well suited for multi-processor systems for software level parallelism. Our quad-Microblaze architecture achieved 75-80% performance improvement compared to its single Microblaze counterpart. Moreover, the quad- Microblaze design is faster than the single-powerPC implementation on FPFA. Therefore, multi-processor architecture with customised coprocessors are e ective for implementing custom parallel architecture to achieve real time image process- ing. |
|
dc.format.extent |
x, 58p. : ill. (some col.) |
en_US |
dc.language.iso |
en |
en_US |
dc.subject |
ELECTRONIC AND TELECOMMUNICATION ENGINEERING - Thesis |
|
dc.subject |
INTEGRATED CIRCUITS - FPGA |
|
dc.subject |
FIELD-PROGRAMMABLE GATE ARRAY |
|
dc.title |
Performance evaluation of vision algorithms on FPGA |
|
dc.type |
Thesis-Abstract |
|
dc.identifier.faculty |
Engineering |
en_US |
dc.identifier.degree |
MSc |
en_US |
dc.identifier.department |
Department of Electronic and telecommunication |
en_US |
dc.date.accept |
2010-07 |
|
dc.identifier.accno |
96427 |
en_US |